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INTEGRATED CIRCUITS
DATA SHEET
SAA7197 Clock Generator Circuit for desktop video systems (CGC)
Product specification File under Integrated Circuits, IC22 August 1996
Philips Semiconductors
Product specification
Clock Generator Circuit for desktop video systems (CGC)
FEATURES * Suitable for Desktop Video systems * Two different sync sources selectable * PLL frequency multiplier to generate 4 times of input frequency * Dividers to generate clocks LLCA, LLCB, LLC2A and LLC2B (2nd and 4th multiples of input frequency) * PLL mode or VCO mode selectable * Reset control and power fail detection QUICK REFERENCE DATA SYMBOL VDDA VDDD IDDA IDDD VLFCO fi VI VO Tamb PARAMETER analog supply voltage (pin 5) digital supply voltage (pins 8, 17) analog supply current digital supply current LFCO input voltage (peak-to-peak value) input frequency range input voltage LOW input voltage HIGH output voltage LOW output voltage HIGH operating ambient temperature range MIN. 4.5 4.5 3 10 1 5.5 0 2.0 0 2.6 0 TYP. 5.0 5.0 - - - - - - - - - GENERAL DESCRIPTION
SAA7197
The SAA7197 generates all clock signals required for a digital TV system suitable for the SAA719x family. The circuit operates in either the phase-locked loop mode (PLL) or voltage controlled oscillator mode (VCO).
MAX. 5.5 5.5 9 60 VDDA 8.0 0.8 VDDD 0.6 VDDD 70 V V
UNIT
mA mA V MHz V V V V C
ORDERING INFORMATION EXTENDED TYPE NUMBER SAA7197P SAA7197T PACKAGE PINS 20 20 PIN POSITION DIP SO MATERIAL plastic plastic CODE SOT146-1 SOT163-1
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Philips Semiconductors
Product specification
Clock Generator Circuit for desktop video systems (CGC)
BLOCK DIAGRAM
SAA7197
handbook, full pagewidth
V DDA 5
V DDD1 V DDD2 8 17
MS
1
SAA7197
LOOP FILTER MS = LOW VCO FREQUENCY DIVIDER 1:2 FREQUENCY DIVIDER 1:2 DELAY PRE-FILTER AND PULSE SHAPER 7 10 14 20 15 LLCA LLCB LLC2A LLC2B CREF
PHASE DETECTOR
LFCO
11
POWER-ON RESET
12
LFCO2 19 CE 2 16 LFCOSEL PORD V SSA V SSD 3 4 6, 9, 13, 18
RESN
MEH461
Fig.1 Block diagram.
FUNCTION DESCRIPTION The SAA7197 generates all clock signals required for a digital TV system suitable for the SAA719x family consisting of an 8-bit analog-to-digital converter (ADC8), digital video multistandard decoder, square pixel (DMSD-SQP), digital video colour space converter (DCSC) and optional extensions. The SAA7197 completes a system for Desktop Video applications in conjunction with memory controllers. The input signal LFCO is a digital-to-analog converted signal provided by the DMDS-SQPs horizontal PLL. It is the multiple of the line frequency: 7.38 MHz = 472 x fH in 50 Hz systems 6.14 MHz = 360 x fH in 60 Hz systems LFCO2 (TTL-compatible signal from an external reference source) can be applied to pin 19 (LFCOSEL = HIGH).
The input signal LFCO or LFCO2 is multiplied by factors 2 or 4 in the PLL (including phase detector, loop filter, VCO and frequency divider) and output on LLCA (pin7), LLCB (pin 10), LLC2A (pin 14) and LLC2B (pin 20). The rectangular output signals have 50% duty factor. Outputs with equal frequency may be connected together externally. The clock outputs go HIGH during power-on reset (and chip enable) to ensure that no output clock signals are available the PLL has locked-on. Mode select MS The LFCO input signal is directly connected to the VCO at MS = HIGH. The circuit operates as an oscillator and frequency divider. This function is not tested.
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Philips Semiconductors
Product specification
Clock Generator Circuit for desktop video systems (CGC)
Source select LFCOSEL Line frequency control signal LFCO (pin 11) is selected by LFCOSEL = LOW. LFCOSEL = HIGH selects LFCO2 input signal (pin 19). This function is not tested. Chip enable CE The buffer outputs are enabled and RESN set HIGH by CE = HIGH (Fig.4). CE = LOW sets the clock outputs HIGH and RESN output LOW. CREF output 2 fLFCO output to control the clock dividers of the DMSD-SQP chip family. Power-on reset
SAA7197
Power-on reset is activated at power-on, when the supply voltage decreases below 3.5 V (Fig.4) or when chip enable is done. The indicator output RESN is LOW for a time determined by capacitor on pin 3. The RESN signal can be applied to reset other circuits of this digital TV system. The LFCO or LFCO2 input signals have to be applied before RESN becomes HIGH.
PINNING SYMBOL MS CE PORD VSSA VDDA VSSD1 LLCA VDDD1 VSSD2 LLCB LFCO RESN VSSD3 LLC2A CREF LFCOSEL VDDD2 VSSD4 LFCO2 LLC2B Note 1. MS and LFCO2 functions are not tested. LFCO2 is a multiple of horizontal frequency. PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DESCRIPTION mode select input (LOW = PLL mode)(1) chip enable /reset (HIGH = outputs enabled) power-on reset delay, dependent on external capacitor
PIN CONFIGURATION
halfpage
analog ground (0 V) analog supply voltage (+5 V) digital ground 1 (0 V) line-locked clock output signal (4 times fLFCO) digital supply voltage 1 (+5 V) digital ground 2 (0 V) line-locked clock output signal (4 times fLFCO) line-locked frequency control input signal 1 reset output (active-LOW, Fig.4) digital ground 3 (0 V) line-locked clock output signal 2A (2 times fLFCO) clock reference output, qualifier signal (2 times fLFCO) LFCO source select (LOW = LFCO selected)(1) digital supply voltage 2 (+5 V) digital ground 4 (0 V) line-locked frequency control input signal 2(1) line-locked clock output signal 2B (2 times fLFCO)
MS CE PORD VSSA VDDA VSSD1 LLCA VDDD1 VSSD2
1 2 3 4 5
20 LLC2B 19 LFCO2 18 VSSD4 17 VDDD2 16 LFCOSEL
SAA7197
6 7 8 9 15 CREF 14 LLC2A 13 VSSD3 12 RESIN 11 LFCO
MGL505
LLCB 10
Fig.2 Pin configuration.
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Philips Semiconductors
Product specification
Clock Generator Circuit for desktop video systems (CGC)
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); ground pins as well as supply pins together connected. SYMBOL VDDA VDDD Vdiff GND VO Ptot Tstg Tamb VESD Note PARAMETER analog supply voltage (pin 5) digital supply voltage (pins 8 and 17) difference voltage VDDA - VDDD output voltage (IOM = 20 mA) total power dissipation (DIL20) storage temperature range operating ambient temperature range electrostatic handling(1) for all pins MIN. -0.5 -0.5 - -0.5 0 -65 0 -
SAA7197
MAX. 7.0 7.0 100 VDDD 1.1 150 70 tbf V V
UNIT
mV V W C C V
1. Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is recommended to take normal handling precautions appropriate to "Handling MOS devices". CHARACTERISTICS VDDA = VDDD = 4.5 to 5.5 V; fLFCO = 5.5 to 8.0 MHz and Tamb = 0 to 70 C unless otherwise specified. SYMBOL VDDA VDDD IDDA IDDD Vreset V11 Vi fLFCO C11 VIL VIH fLFCO2 ILI CI VOL VOH td PARAMETER analog supply voltage (pin 5) digital supply voltage (pins 8 and 17) analog supply current (pin 5) digital supply current (I8 + I17) power-on reset threshold voltage note 1 Fig.4 CONDITIONS MIN. 4.5 4.5 3 10 - TYP. 5.0 5.0 - - 3.5 - - - - - - - - - - - - - MAX. 5.5 5.5 9 60 UNIT V V mA mA V
Input LFCO (pin 11) DC input voltage input signal (peak-to-peak value) input frequency range input capacitance 0 1 5.5 - VDDA VDDA 8.0 10 V V MHz pF
Inputs MS, CE, LFCOSEL and LFCO2 (pins 1, 2, 16 and 19); note 3 input voltage LOW input voltage HIGH input frequency range for LFCO2 input leakage current input capacitance LFCOSEL others Output RESN (pin 12) output voltage LOW output voltage HIGH RESN delay time IOL = 2 mA IOH = -0.5 mA C3 = 0.1 F; Fig.4 0 2.4 20 0.4 VDDD 200 V V ms 0 2.0 5.5 50 - - 0.8 VDDD 8.0 150 10 5 V V MHz A A pF
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Philips Semiconductors
Product specification
Clock Generator Circuit for desktop video systems (CGC)
SAA7197
SYMBOL Output CREF (pin 15) VOL VOH fCREF CL tSU tHD VOL VOH tcomp fLL
PARAMETER
CONDITIONS
MIN. - -
TYP.
MAX.
UNIT
output voltage LOW output voltage HIGH output frequency CREF output load capacitance set-up time hold time
IOL = 2 mA IOH = -0.5 mA Fig.3 Fig.3; note 1 Fig.3; note 1
0 2.4 - 15 12 4
0.6 VDDD 40 - -
V V MHz pF ns ns
2 fLFCO(2) - - - - - - 4 fLFCO(2) 4 fLFCO(2) 2 fLFCO(2) 2 fLFCO(2) - 50 5 60
Output signals LLCA, LLCB, LLC2A and LLC2B (pins 7, 10, 14, and 20); note 3 output voltage LOW output voltage HIGH composite rise time output frequency LLCA output frequency LLCB output frequency LLC2A output frequency LLC2B tr, tf tLL Notes 1. fLFCO = 7.0 MHz and output load 40 pF (Fig.3). VSSA and VSSD short connected together. 2. tcomp is the rise time from LOW of all clocks to HIGH of all clocks (Fig.3) including rise time, skew and jitter components. Measurements taken between 0.6 V and 2.6 V. Skew between two LLx clocks will not deviate more than 2 ns if output loads are matched within 20%. 3. MS and LFCO2 functions not tested. rise and fall times duty factor LLCA, LLCB, LLC2A and LLC2B (mean values) Fig.3 note 1; Fig.3; at 1.5 V level IOL = 2 mA IOH = -0.5 mA Fig.3 0 2.6 - - - - - 40 0.6 VDDD 8 V V ns MHz MHz MHz MHz ns %
Fig.3; notes 1 and 2 -
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Philips Semiconductors
Product specification
Clock Generator Circuit for desktop video systems (CGC)
SAA7197
handbook, full pagewidth
CREF
2.4 V 0.6 V t HD t SU t LLC t LLC H t LLC L 2.6 V 1.5 V 0.6 V tf t LLC2 t LLC2 H t LLC2 L tr t HD
LLCA LLCB
LLC2A LLC2B
tr
2.6 V 1.5 V 0.6 V t comp tf
MEH466
Fig.3 Output timing.
August 1996
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Philips Semiconductors
Product specification
Clock Generator Circuit for desktop video systems (CGC)
SAA7197
handbook, full pagewidth
V DDA V
DDD
+3.5 V 0V power-on oscillation disturbed
LFCO
oscillation
RESN
td normal operation
td normal operation
LLCA LLCB LLC2A LLC2B power failure starts a new reset procedure
PLL lock-on clock HIGH during internal reset reset time
MEH467
Fig.4 Reset procedure.
handbook, full pagewidth
1 2 16 19 MS CE LFCOSEL LFCO2
VDDD
VDDD
7 10 14 15 20
LLCA LLCB LLC2A LLC2B CREF
VSSD
VSSD VDDD
11 LFCO
12 RESN
VSSD
MEH469
Fig.5 Internal circuit.
August 1996
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Philips Semiconductors
Product specification
Clock Generator Circuit for desktop video systems (CGC)
PACKAGE OUTLINES DIP20: plastic dual in-line package; 20 leads (300 mil)
SAA7197
SOT146-1
D seating plane
ME
A2
A
L
A1
c Z e b1 b 20 11 MH wM (e 1)
pin 1 index E
1
10
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.020 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D
(1)
E
(1)
e 2.54 0.10
e1 7.62 0.30
L 3.60 3.05 0.14 0.12
ME 8.25 7.80 0.32 0.31
MH 10.0 8.3 0.39 0.33
w 0.254 0.01
Z (1) max. 2.0 0.078
26.92 26.54 1.060 1.045
6.40 6.22 0.25 0.24
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT146-1 REFERENCES IEC JEDEC EIAJ SC603 EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-05-24
August 1996
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Philips Semiconductors
Product specification
Clock Generator Circuit for desktop video systems (CGC)
SAA7197
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A X
c y HE vMA
Z 20 11
Q A2 A1 pin 1 index Lp L 1 e bp 10 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z
(1)
0.9 0.4 0.035 0.016
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
8o 0o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-01-24 97-05-22
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Philips Semiconductors
Product specification
Clock Generator Circuit for desktop video systems (CGC)
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. SO REFLOW SOLDERING Reflow soldering techniques are suitable for all SO packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement.
SAA7197
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. WAVE SOLDERING Wave soldering techniques can be used for all SO packages if the following conditions are observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The longitudinal axis of the package footprint must be parallel to the solder flow. * The package footprint must incorporate solder thieves at the downstream end. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
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Philips Semiconductors
Product specification
Clock Generator Circuit for desktop video systems (CGC)
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7197
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
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Philips Semiconductors
Product specification
Clock Generator Circuit for desktop video systems (CGC)
NOTES
SAA7197
August 1996
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Philips Semiconductors
Product specification
Clock Generator Circuit for desktop video systems (CGC)
NOTES
SAA7197
August 1996
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Philips Semiconductors
Product specification
Clock Generator Circuit for desktop video systems (CGC)
NOTES
SAA7197
August 1996
15
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For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
657027/00/01/pp16
Date of release: August 1996
Document order number:
9397 750 02438

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